1. Field of the Invention
The invention relates to improving computer system bus performance, and more particularly, to circuitry that prevents a microprocessor system from posting write cycles to a bus if another bus master is requesting the bus.
2. Description of the Related Art
The performance demands on personal computers are ever increasing. It has been determined that a major bottleneck in improving performance is the capability to perform input/output (I/O) operations. Processor speeds continue to increase at a great rate and memory speeds and architectures can partially keep pace. However, the speed of I/O operations, such as disk and local area network (LAN) operations, has not kept pace. The increasing complexity of video graphics used in personal computers is also demanding greater performance then can be conventionally provided.
Some of the problems were in the bus architecture used in IBM PC-compatible computers. The EISA architecture provided some improvement over the ISA architecture of the IBM PC/AT, but more performance was still required. To this end Intel Corporation, primarily, developed the Peripheral Component Interconnect (PCI) bus. The PCI bus is a mezzanine bus between the host or local bus in the computer, to which the processor and memory are connected, and the I/O bus, such as ISA or EISA. For more details on the PCI bus, reference to the PCI Standard Version 2.0, from the PCI Special Interest Group in care of Intel Corp., which is hereby incorporated by reference, is advised. The bus was designed to have a high throughput and to take advantage of the increasing number of local processors that support I/O functions. For example, most disk controllers, particularly SCSI controllers, and network interface cards (NICs) include a local processor to relieve demands on the host processor. Similarly, video graphics boards often include intelligent graphics accelerators to allow higher level function transfer. Typically these devices have the capability of operating as bus masters, to allow them to transfer data at the highest possible rates.
Because of the number of potential devices trying to be bus masters, an arbitration scheme is required. A common arbitration scheme is least-recently-used (LRU). In certain cases, such as described in U.S. Pat. No. 5,535,395, entitled "Prioritization of Microprocessors in Multiprocessor Computer Systems," filed on Oct. 2, 1992, which is hereby incorporated by reference, the LRU scheme is modified so that the LRU of just the various requestors is utilized. This avoids potential deadlock conditions.
Another arbitration scheme is described in U.S. patent application Ser. No. 08/187,843, entitled "Bus Master Arbitration Circuitry Having Improved Prioritization," filed on Jan. 28, 1994, hereby incorporated by reference. The '843 application described an arbiter for the PCI bus which minimizes thrashing on a bus due to a retry generated by a target device. According to the PCI standard, responding target devices may abort a cycle by generating a retry to the bus master. By so aborting the operation, other bus masters are allowed to gain access to the bus while the target device that generated the retry is given the opportunity to clear whatever condition caused it to issue the retry. The '843 application described an arbiter which masked further requests from the retried master to prevent thrashing of the bus. However, the high priority of the masked request is maintained in subsequent arbitration cycles.
In the computer system described in the '843 application, other arbiters also existed for performing arbitration for other resources. The computer system included a PCI bus, an EISA bus, and a DMA controller. The multiple arbiters worked together to arbitrate access to the PCI and EISA buses.